Pulse generators

ABSTRACT

The pulse generator is described in which a pair of storage registers are connected in parallel with one another and initially loaded such that a first of the registers has a substantially smaller unfilled capacity than the second register. A clock generator then feeds pulses equally to the two registers to progressively reduce the unfilled capacity of each register and when the first register has been filled a &#39;&#39;full&#39;&#39; signal is generated which causes immediate reloading of the first register to the same initial capacity. A logic circuit connected to selected bit outputs of the first register generates a pulse, or a pulse pattern, during the time taken to fill the first register and when the second register has been filled a second &#39;&#39;full&#39;&#39; signal inhibits the feeding of further clock pulses to the register. The total number of pulse cycles is therefore the ratio of the initially unfilled capacity of the second register to the unfilled capacity of the first register.

United States Patent Woodcock [s41 PULSE GENERATORS [72] inventor:Terence Keith Woodcock, Barton-le-Clay,

England [73] Assignee: British Aircraft Corporation Limited, London,England [22] Filed: Oct. 6, 1970 [21] Appl. No.: 78,410

[52] US. Cl. ..328/59, 328/37, 328/61, 328/188 [51] Int. Cl. ..H03k 1/00[58] Field ofSearch ,.328/37,6l,59, 187, 188,189; 307/221, 271

[56] References Cited UNITED STATES PATENTS 3,411,094 11/1968 Martinek"328/37 3,439,279 4/1969 Guanella.. ...328/37 X 3,464,018 8/1969 Cliff..328/6l 1 Mar. 7, 1972 Primary Examiner-John Zazworsky Attorney-Kemon,Palmer & Estabrook ABSTRACT The pulse generator is described in which apair of storage registers are connected in parallel with one another andinitially loaded such that a first of the registers has a substantiallysmaller unfilled capacity than the second register. A clock generatorthen feeds pulses equally to the two registers to progressively reducethe unfilled capacity of each register and when the first register hasbeen filled a full signal is generated which causes immediate reloadingof the first register to the same initial capacity. A logic circuitconnected to selected bit outputs of the first register generates apulse, or a pulse pattern, during the time taken to fill the firstregister and when the second register has been filled a second fullsignal inhibits the feeding of further clock pulses to the register. Thetotal number of pulse cycles is therefore the ratio of the initiallyunfilled capacity of the second register to the unfilled capacity of thefirst register.

3 Claims, 2 Drawing Figures [Add/ 5954 I Start Command 6/ 0/; Address 2w, 2 F 11/ 2 M/ Paz Add/e933 Peg/ tep3 fill/3 M2 Bl Add/ 9995 I ResetMfr/bit Patented March 7, 1972 2 Sheets-Sheet 1 Inventor fins/we K.Waoocoe p v54! Allorneyg Patented March 7, 1972 2 Sheets-Sheet I nvenlorflaw/van. K W -K Allorneym PULSE GENERATORS When automatic testequipment is operated in a self-test mode, a pulse generator is normallyprovided to generate pulses which simulate those which would otherwisebe provided by the system under test. The pulse generator may also beused during prime testing of the equipment, and to generate pulses forthe test inputs of subsystems.

In such equipment, it is clearly advantageous to have a pulse generatorwhich is driven from a single clock but which nevertheless can produce apredetermined cyclic pulse pattern depending on the test beingsimulated. It is also preferable to run the clock substantiallycontinuously during a test,

and frequently it is important that the exact number of pulses,

or pulse patterns, generated during a test should be controlled.

According to the present invention a pulse generator comprises a pair ofstorage registers initially loaded such that a first of the registershas a substantially smaller unfilled capacity than the second register,a clock for feeding pulses equally to the two registers to progressivelyreduce the unfilled capacity of each register, means responsive to thefilling of the first register for momentarily inhibiting the feeding ofclock pulses to the registers and immediately reloading the firstregister to the same initial capacity, a logic circuit connected toselected bit outputs of the first register to generate an output pulse,or pulse pattern, during the time taken to fill the first register, andmeans responsive to the filling of the second register to inhibit thefeeding of further pulses to the registers whereby the total number ofoutput pulses, or pulse patterns, generated is the ratio of theinitially unfilled capacity of the second register to the initiallyunfilled capacity of the first register.

In a preferred embodiment of the invention a full signal is generatedwhenever the first register is filled and this signal momentarilyinhibits the feeding of clock pulses and causes a third register(initially loaded to the same capacity as the first register) to emptyits contents into the first register. The third register acts as atemporary store and has a parallel input from an address. During thesubsequent filling of the first register in the next cycle, the thirdregister is again loaded to the same capacity from the address.

During the reloading of the first register the clock is momentarilyinhibited, and thus the period between the successive first registerfull signals is determined by the unfilled capacity of the firstregister (and hence of the third register), the clock pulse ratefrequency, and the clock inhibit time during the reload. Thus simply byvarying the initial loading of the first and third registers, the periodof the successive output pulses, or pulse patterns can be varied.

One example of the invention will now be described with reference to theaccompanying drawings in which:

FIG. 1 is a logic diagram of a circuit for generating a pulse pattern.

FIG. 2 is a logic diagram of the pattern generator shown in FIG. 1.

Referring to FIG. ll, storage register 2 and storage register 3 comprisefirst and second storage registers for controlling the pattern producedby the pattern generator. Each of these two registers are capable ofaddition as well as being able to be parallel loaded from an address.Register 1, on the other hand, is a memory which is capable of beingparallel loaded from an address and acts as a temporary store for thebits to be loaded in register 2.

Registers l and 2 are initially filled to a predetermined capacity inresponse to a load command from address 1. This command enables register1 which is parallel loaded from address 4, and the load command is alsotransmitted to address 2 through the OR-gate G1 to enable register 2.Register 2 is, therefore, parallel loaded from register 1 and istherefore filled to the same capacity as register 1.

At the same time, register 3 is parallel loaded from address 5 inresponse to a load command from address 3, but the unfilled capacity ofregister 3 is arranged to be much higher than that of register 2.

In response to a start command applied to bistable Bl, the clock ANDgate is enabled and pulses are simultaneously fed to registers 2 and 3.Since register 2 has the smaller unfilled capacity, this will fillbefore register 3. Selected bit outputs from register 2 are fed to thepattern generator so that during the time taken to fill register 2 apulse pattern is fed out of the generator. A full 2 signal signifiesthat register 2 has been filled, and this switches monostable Ml so thata positive pulse is fed along path ill and a negative pulse along path10. The negative pulse momentarily inhibits the clock AND gate and thepositive pulse is fed to the OR'-gate G1. The output from the OR gateenables the register 2 from address 2 and, register 2 is thereforeimmediately reloaded from register 11.

This cycle of events is repeated until register 3 is filled when a full3 signal switches monostable M2 to reset the bistable B1 and therebypermanently inhibit further clock pulses until another start commandsignal is generated. Clearly, the number of pulse patterns produced inthe time taken to fill register 3 will be the ratio of the initiallyunfilled capacity of the register 3 to the unfilled capacity of register2. This ratio can easily be varied. The period of the successive pulsepatterns, i.e., the period between successive full 2 signals isdetermined by the unfilled capacity of register 2, the clock pulsefrequency and the clock inhibit time during reload. Hence, by varyingthe initial loading of registers 1 and 2 from address 4, the period ofthe pulse pattern is easily varied.

Referring now to FIG. 2, one example of a suitable pattern generator isshown in detail. The selected bit outputs from register 2 are taken toAND gates which are also fed with the inverted or normal outputs frombistables B3, B4, B5 and B6. Additional bistables and AND gates can beconnected in a similar fashion to the remaining bit outputs of register2. The particular pattern to be generated is set by feedingpredetermined address signals to the bistables B3-B6. The outputs fromB3 and B5 control a start gate so that the bistable B7 is set when thedirect and complementary bit outputs from register 2 signify that thecount in register 2 has reached a particular count. As the countproceeds, bistables B4 and B6 produce signals which enables a stop gateto reset the bistable B7. Any desired pattern can, therefore, beproduced by connecting selected bit outputs into the circuit. The outputfrom the bistable B7 comprises the final output of the pattern generatorand this is fed to an output stage which will include power amplifiersand impedance convertors.

One numerical example will now be described with reference to FIG. 1.Consider register 2 to have a capacity of 10,000 and register 3 to havea capacity of 100,000. Register 2 is initially loaded with 7,500 andregister 3 is initially loaded with 20,000. For a clock rate of l mc./s.the unfilled capacity of register 2 (which must be equal to register 1)is filled in 2.5 ms. Thus, the desired pulse pattern will be producedduring this 2.5 ms. As mentioned above, the number of times the patternwill be repeated depends on the ratio of the unfilled capacities ofregister 2 and register 3. In this example the pattern will, therefore,be repeated 32 times with a frequency of 400 c./s.

It is possible to vary the whole time-base of the pulse pattern byadding a further pair of registers corresponding to registers l and 2.If the basic clock is changed to 10 mc./s. and the additional registersare loaded with out of atotal capacity of 100, then the additionalregister 2 would produce 4,000 pulse patterns at a frequency of 500kc./s., while the 32 pulse patterns from the original register 2 wouldhave a pulse rate frequency of 4,000 c./s.

I claim:

1. A method of deriving a pulse train having a predetermined number ofpulses comprising: initially loading a pair of storage registers suchthat a first of the registers has a substantially smaller unfilledcapacity than the second register, feeding clock pulses equally to thetwo registers to progressively reduce the unfilled capacity of eachregister, momentarily inhibiting the feeding of clock pulses to theregisters in response to the filling of the first register andimmediately reloading the first register to the same initial capacity,feeding selected bit outputs of the first register to a logic circuit togenerate an output pulse, or a pulse pattern, during the time taken tofill the first register, and inhibiting the feeding of further pulses tothe registers in response to the filling of the second register wherebythe total number of output pulses, or pulse patterns, generated is theratio of the initially unfilled capacity of the second register to theunfilled capacity of the first register.

2. A pulse generator for generating a pulse train having a predeterminednumber of pulses, or pulse patterns, comprising a pair of storageregisters, a clock for feeding pulses equally to the two registers,means responsive to the filling of a first of the registers formomentarily inhibiting the clock pulses to the registers and immediatelyreloading the first register, a logic circuit connected to selected bitoutputs of the first register to generate an output pulse, or a pulsepattern, during the time taken to fill the first register, and meansresponsive to the filling of the second register to inhibit the feedingof further pulses to the registers, whereby, if the two registers arerepeatedly loaded such that the first register has a substantiallysmaller unfilled capacity than the second register, the total number ofoutput pulses, or pulse patterns generated is the ratio of the initiallyunfilled capacity of the second register to the initially unfilledcapacity of the first register.

3. A pulse generator according to claim 2 further including a thirdregister, so arranged that the contents of the third register areparallel loaded into the first register in response to a signalsignifying that the first register has been filled.

I it i

1. A method of deriving a pulse train having a predetermined number ofpulses comprising: initially loading a pair of storage registers suchthat a first of the registers has a substantially smaller unfilledcapacity than the second register, feeding clock pulses equally to thetwo registers to progressively reduce the unfilled capacity of eachregister, momentarily inhibiting the feeding of clock pulses to theregisters in response to the filling of the first register andimmediately reloading the first register to the same initial capacity,feeding selected bit outputs of the first register to a logic circuit togenerate an output pulse, or a pulse pattern, during the time taken tofill the first register, and inhibiting the feeding of further pulses tothe registers in response to the filling of the second register wherebythe total number of output pulses, or pulse patterns, generated is theratio of the initially unfilled capacity of the second register to theunfilled capacity of the first register.
 2. A pulse generator forgenerating a pulse train having a predetermined number of pulses, orpulse patterns, comprising a pair of storage registers, a clock forfeeding pulses equally to the two registers, means responsive to thefilling of a first of the registers for momentarily inhibiting the clockpulses to the registers and immediately reloading the first register, alogic circuit connected to selected bit outputs of the first register togenerate an output pulse, or a pulse pattern, during the time taken tofill the first register, and means responsive to the filling of thesecond register to inhibit the feeding of further pulses to theregisters, whereby, if the two registers are repeatedly loaded such thatthe first register has a substantially smaller unfilled capacity thanthe second register, the total number of output pulses, or pulsepatterns generated is the ratio of the initially unfilled capacity ofthe second register to the initially unfilled capacity of the firstregister.
 3. A pulse generator according to claim 2 further including athird register, so arranged that the contents of the third register areparallel loaded into the first register in response to a signalsignifying that the first register hAs been filled.